Concurrent Placement and Routing in the Design of Integrated Circuits
نویسندگان
چکیده
For the problem arising in the design of integrated chips, an efficient heuristic approach was proposed. It unites the stages of placing the logical elements (devices) on the chip and performing their detailed routing. At that, it minimizes both the critical (maximum) delay and the chip area required for routing.
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تاریخ انتشار 2002